In order to fabricate integrated circuits, layers provided with different electrical properties are usually applied to semiconductor wafers and patterned lithographically. A lithographic patterning may include applying a photosensitive resist, exposing the resist with a desired structure for the relevant layer, developing the resist, and subsequently transferring the resist mask thus produced into the underlying layer in an etching step.
As the integration densities of integrated circuits continuously increase, positional accuracy requirements of a structure to be projected onto the semiconductor substrate also increase. When preliminary layers have already been transferred in underlying layers, e.g., in a lithographic projection step, it is necessary to account for stricter tolerance limits with regard to the mutual orientation of the structure to be projected onto the substrate relative to the structures of the aforementioned preliminary layers to ensure functionality of the circuit.
Dense line-space patterns are formed, for instance, in the area of fabrication of dynamic random access memories (DRAM) with line widths of 70, 90, or 110 nm, for example, in the region of the first circuit layers. In modem technologies for DRAM fabrication, the accuracy required for the orientation of two structures, also referred to as the overlay budget, will decrease due to decreasing structure resolutions. Thus, for example, the tolerable positional inaccuracy is only approximately 20 nm in the case of the 100 nm process line. Current and future process lines are thus sensitive to errors in the positional accuracy.
For the lithographic projection step, which may be performed, e.g., in a wafer stepper or scanner, alignment sequences are therefore provided before the beginning of the respective exposures. The alignment marks are typically arranged in the edge regions of the masks providing the relevant structure. During the exposure, the alignment marks are transferred in the sawing frame separating the individual exposure fields on the wafer. The alignment marks make it possible to determine the position of the structures formed on the wafer, or, as a result of determining the position of the alignment marks, possible to deduce the accurate positioning and orientation of the structure for the integrated circuit.
The exposure of the individual exposure fields is usually performed such that the top side of the semiconductor wafer is subdivided into a pattern of exposure fields in the form of a matrix or grid and is successively exposed by the wafer scanner or the wafer stepper.
The positional accuracy of two layers lying one above the other is normally determined by overlay targets during the production of integrated circuits. The targets are two partial structures each imaged separately onto each of the layers. The first partial structure may comprise a rectangular structure element surrounded by a frame-type second partial structure. Overlay targets are usually arranged together with other alignment marks in the sawing frame region. The structure described above is known as a box-in-box mark or a box-in-frame mark. The offset of the individual partial structures with respect to one another is usually measured by an overlay measuring apparatus, for example, an optical microscope.
In the exposure of a semiconductor wafer by a wafer scanner, a number og effects may lead to overlay errors. These overlay errors can generally be assigned to two categories of error sources. First, errors may occur which arise during the exposure within an exposure field. These error sources are usually referred to as intra-field error or field error. Second, error sources may be caused by the division of the semiconductor wafer into individual exposure fields and may be different for each exposure field. These error sources are usually referred to as inter-field error or grid error.
The orientation or alignment of the substrate in the exposure apparatus with respect to the projection optical arrangement (i.e., the projection lenses, the respective mask to be projected, apertures, and the illumination source, etc.) is carried out by comparing the alignment marks with reference marks. Such reference marks are often inserted by the lens system with respect to a detector.
The way the alignment method (alignment or overlay) is specifically carried out depends on the apparatus manufacturers. Based on the mark comparison, an offset between the actual alignment mark position and the ideal position of the reference mark is ascertained, modeled, and corrected.
A problem to which little consideration has been given hitherto is the degree of positional accuracy of different structure pattern portions, which can be attained differently within an exposure field. Reasons for this are, in particular, lens imaging errors such as, for example, the distortions called coma, three-leaf clover, astigmatism, etc., which are generally referred to as aberration errors.
One problematic effect is that the size of the imaging error of a structure is dependent on the respective form, orientation, and size of the structure. Thus, for example, dense line-space structures with very small structure dimensions are provided with a different offset with respect to an ideal position in an exposure with a perfect lens than, for example, the alignment marks that generally have very large dimensions.
In such cases, the above-mentioned deduction of the positions of the respectively imaged structures from the position determined for the alignment mark during the alignment and the determination of the overlay may be erroneous. This holds true as the structures or structure elements differ from the alignment marks in size, form, and orientation.
In the area of the alignment methods, i.e., in the case of the alignment or overlay of a wafer in the exposure apparatus, overlay measurement marks with a microstructure are known. The microstructure is provided with structure elements representing the semiconductor component of this layer. The overlay measurement marks are thus subject to a different imaging error due to lens distortions than hitherto customary box-in-box or box-in-frame measurement marks. The exposure position determined by alignment mark comparison during the alignment of a substrate subsequently exposed is corrected such that the structures of the individual layers, instead of the overlay measurement marks, are imaged on one another with higher accuracy.
In this case, however, it proves disadvantageous for a determination of the positional accuracy error by the micro-patterned measurement marks for different structures. It is necessary to provide special measurement marks which permit a determination of the overlay or of the positional inaccuracies for the two layers lying one above the other. As a result, the determination of the positional inaccuracies for all layers of the integrated circuit, particularly in an evaluation of a new process line, is very time-consuming. In conventional measuring apparatuses, the frequently changing patterning are associated with varying contrast or intensity conditions, which impedes the measurability of the micro-patterned measurement marks.
Therefore, a method for an integrated circuit with one or a plurality of layers that enable a simple correction of the structure-dependent positioning errors for each layer is desirable.